Tungsten CMP Slurry: The Complete Technical and Procurement Guide

1. What Is Tungsten CMP Slurry?

Chemical mechanical planarization (CMP) is the only process in semiconductor manufacturing capable of achieving the global planarity — flatness measured in angstroms across a 300 mm wafer — that advanced multilayer interconnect structures require. CMP combines controlled chemical reactions with mechanical abrasion simultaneously, removing material from the highest topographic features while leaving recessed areas largely untouched. Among all CMP applications, the planarization of tungsten films is one of the most technically demanding and economically significant.

Tungsten CMP slurry is the engineered aqueous dispersion that mediates this planarization step. Applied between the rotating polishing pad and the rotating wafer surface, it performs two simultaneous functions: it chemically converts the surface of the metallic tungsten film into a softer, water-soluble oxide compound, and it mechanically abrades and removes that converted layer through the action of suspended submicron particles. The net result is controlled tungsten removal at rates that can exceed 3,000 Å/min — roughly equivalent to removing a tungsten film 30 nm thick every 60 seconds — with a surface finish capable of supporting sub-10 nm feature lithography in the subsequent process step.

The formulation of a tungsten CMP slurry is a precision exercise in colloidal chemistry. A production slurry contains abrasive particles (most commonly silicon dioxide, SiO₂), an oxidizing agent (most commonly hydrogen peroxide, H₂O₂), a metal ion catalyst (most commonly ferric nitrate, Fe(NO₃)₃), and a suite of stabilizers, complexing agents, and pH modifiers that keep the formulation chemically stable during storage, shipping, and delivery to the point of use at the polishing tool. Each component contributes to the slurry’s removal rate, its selectivity to dielectric materials below the tungsten film, its defect performance, and its shelf life.

The choice of tungsten CMP slurry has direct consequences for device yield, process throughput, and cost of ownership. A slurry that delivers insufficient removal rate forces longer polish times that reduce wafer-per-hour throughput on expensive CMP tools. A slurry with poor selectivity removes excess dielectric and compromises device electrical performance. A slurry with inadequate defect control generates microscratch counts that fail inspection limits and require additional cleaning steps or, in the worst case, cause die-level failures. Selecting the right slurry and the right supplier requires systematic evaluation across all these dimensions.

2. Why Tungsten in Semiconductor Fabrication?

Tungsten has served as the primary metal for semiconductor contact plugs and vias since the late 1980s, and it remains dominant in this role across the full spectrum of production technology nodes in 2026. Its persistence is not inertia — it reflects a combination of physical, chemical, and process properties that no alternative metal has fully replicated in a production context.

Physical and Electrical Properties

Tungsten’s most distinctive property is its melting point of 3,422℃ — the highest of any pure metal. This thermal stability ensures that tungsten remains dimensionally and electrically stable through every subsequent thermal process step after deposition, including high-temperature dielectric anneal sequences that would cause other metals to migrate, agglomerate, or interdiffuse. Its bulk resistivity of approximately 5.3 μΩ·cm (for chemical vapor deposited material) is higher than copper or cobalt, but is more than adequate for the short, small-diameter contacts that tungsten fills.

The defining process advantage of tungsten is its gap-fill capability. CVD tungsten, deposited from tungsten hexafluoride (WF₆) precursor in a hydrogen-reduction process, nucleates and grows conformally, filling contact and via features with aspect ratios of 8:1, 10:1, or higher without void formation. No other metal offers this combination of conformal deposition, thermal stability, and established integration with the surrounding TiN/Ti liner stack that serves as the adhesion and barrier layer.

Where Tungsten Appears in Integrated Circuit Structures

In a leading-edge logic chip, tungsten occupies three structural roles. At the middle of line (MOL), it fills the contact vias that connect the source, drain, and gate terminals of individual transistors to the first metal interconnect layer. At the replacement metal gate (RMG) level, tungsten (or tungsten in combination with a thin work function metal layer) fills the gate electrode trench after the sacrificial polysilicon is removed and the high-k dielectric is deposited. At the first local interconnect level (LI or M0), tungsten sometimes serves as the conductor material before transitioning to copper or cobalt for higher metal levels.

In 3D NAND flash memory, tungsten replaces polysilicon as the wordline conductor in the multi-layer gate stack, a transition that has improved device speed and reliability while creating new CMP challenges. In DRAM, tungsten fills the buried wordline trenches and the storage node contacts that form the core of each memory cell.

The Competitive Landscape: Cobalt and Ruthenium

Cobalt and ruthenium have emerged as candidates to replace tungsten at the most advanced nodes (sub-3 nm logic, future DRAM generations) where their lower resistivity in scaled-down geometries offers a performance advantage. Leading foundries have already deployed cobalt at certain metal levels in their most advanced logic products. However, tungsten remains the dominant contact and gate fill metal for the overwhelming majority of wafers in production today, and the CMP consumables ecosystem built around it — slurries, pads, cleaners, endpoint sensors — will continue to support high-volume production through the end of this decade and into the next.

3. The Chemistry Behind Tungsten CMP

The tungsten CMP removal mechanism is a cyclical electrochemical-mechanical process that operates continuously across the wafer surface during polishing. Understanding it at the reaction level is essential for interpreting removal rate data, diagnosing process anomalies, and making informed choices about slurry formulation parameters.

Phase 1: Chemical Oxidation of Tungsten

The chemical half of the process begins when the oxidizing agents in the slurry react with the exposed metallic tungsten film. The primary oxidizer, hydrogen peroxide (H₂O₂), converts tungsten metal at the surface into tungsten trioxide (WO₃). A simplified overall reaction is:

The rate of WO₃ formation depends on H₂O₂ concentration, temperature, pH, and the presence of a catalyst. At the concentrations typically used in production slurries (0.3 to 2.0 wt%), H₂O₂ alone generates WO₃ at a rate insufficient for practical throughput. This is where the ferric ion catalyst — most commonly delivered as ferric nitrate (Fe(NO₃)₃) at 10 to 100 parts per million — plays an essential role.

The Fenton-Type Catalytic Cycle

Ferric ions (Fe³⁺) participate in what is known as a Fenton-type catalytic mechanism. In this cycle, Fe³⁺ accepts electrons from H₂O₂ to form ferrous ions (Fe²⁺) and the highly reactive hydroperoxyl radical (HO₂·). The Fe²⁺ ions then react with additional H₂O₂ to regenerate Fe³⁺ and produce hydroxyl radicals (·OH). These hydroxyl radicals are far more powerful oxidizers than H₂O₂ alone, dramatically accelerating tungsten surface oxidation. The iron catalyst is regenerated in this cycle rather than consumed, making even small Fe³⁺ concentrations highly effective.

Phase 2: Mechanical Abrasion and Oxide Removal

Once the WO₃ passivation layer forms on the tungsten surface, the abrasive particles in the slurry — typically fumed or colloidal SiO₂ at 1 to 10 wt% — mechanically abrade and dislodge this oxide. The removed WO₃ dissolves into the slurry’s aqueous phase and is transported away from the polishing zone by hydrodynamic flow between the pad and the wafer. This mechanical removal step re-exposes fresh metallic tungsten to the slurry chemistry, and the oxidation cycle begins again.

The Role of pH

The acidic pH environment (typically pH 2 to 4 for standard formulations) is not arbitrary. It serves three critical functions: it promotes dissolution of the WO₃ reaction product, preventing re-deposition as surface residue; it maintains Fe³⁺ ions in their ionic form (iron precipitates as Fe(OH)₃ above approximately pH 3.5, which can introduce abrasive-type particles that cause scratches); and it controls the surface charge (zeta potential) of the silica abrasive particles, which governs their colloidal stability and interaction with the wafer surface. Slurry pH must be controlled within ±0.2 pH units during manufacturing and monitored continuously through the slurry delivery system at the polishing tool.

4. The Two-Step Tungsten CMP Process

Production tungsten CMP almost universally employs a two-step or two-platen approach, with each step using a slurry specifically formulated for that step’s removal objectives. The distinction between steps is not merely a question of polish time — each step uses a different slurry chemistry, a different selectivity profile, and targets a different remaining film stack.

Some advanced process flows employ a single-step CMP approach using a selectivity-transitioning slurry, or use three-platen schemes that separate endpoint detection, bulk removal, and surface finish steps for maximum control. However, the two-step model remains the dominant architecture across logic, NAND, and DRAM production environments as of 2026.

5. Key Components of Tungsten CMP Slurry

A production tungsten CMP slurry is not a simple mixture of particles in water. It is a precision-engineered colloidal system in which each ingredient serves a defined function, and the interactions between ingredients determine overall polishing performance, stability, and defect outcome. The following breakdown covers each functional component category in turn.

研磨粒子

Silicon dioxide (SiO₂) is the dominant abrasive used in tungsten CMP. It is available in two structural forms with meaningfully different performance characteristics.

ヒュームドシリカ is manufactured by flame hydrolysis of silicon tetrachloride (SiCl₄) at high temperature. The resulting primary particles fuse into branched, chain-like aggregates with a broad particle size distribution (PSD) and irregular morphology. Fumed silica delivers high tungsten MRR due to its high surface area and mechanically aggressive particle shape, but the wide PSD — particularly the tail of oversized agglomerates — creates a risk of micro-scratch generation. Fumed silica slurries require robust filtration systems at the point of use to manage the large-particle tail and maintain acceptable defect levels.

コロイダルシリカ is produced through a wet-chemical process (typically based on the Stöber method or ion-exchange precipitation) that yields nearly spherical particles with a tightly controlled PSD. The narrow, well-characterized particle size results in more predictable polishing kinetics, lower micro-scratch counts, and improved lot-to-lot consistency compared to fumed silica. Colloidal silica formulations are the preferred choice for advanced node applications where post-CMP defect budgets are extremely tight. The trade-off is typically a somewhat lower peak MRR compared to equivalent fumed silica formulations.

Alumina (Al₂O₃) abrasive, with a Mohs hardness of 9 compared to silica’s 7, is used in some Step 2 (barrier) formulations where mechanical aggressiveness against the Ti/TiN liner is needed for acceptable throughput. Alumina-based barrier slurries require careful process parameter optimization to avoid excessive oxide erosion.

酸化剤

過酸化水素（H₂O₂) is the standard oxidizer in commercial tungsten CMP slurries, used at 0.3 to 2.0 wt%. It is low cost, readily available in semiconductor-grade purity (29 – 31% concentration from specialty chemical suppliers), and effective across the acidic pH range used for tungsten CMP. Its principal limitation is stability in the presence of metal ions, heat, and UV radiation — all of which accelerate H₂O₂ decomposition. For this reason, H₂O₂-containing slurries are typically supplied as two-component systems: the abrasive slurry (Component A) and the oxidizer solution (Component B) are shipped and stored separately, then mixed at the point of use at the polishing tool immediately before dispensing. This approach maximizes slurry stability and ensures consistent oxidizer concentration at the wafer surface.

Periodic acid (HIO₄) is an alternative oxidizer used in certain specialty formulations, particularly those targeting neutral or near-neutral pH operation. Periodic acid is more stable than H₂O₂ in aqueous solution at moderate temperatures, enabling single-component slurry packaging in some formulations. However, its higher cost and the contamination risk from iodine-containing decomposition products limit its adoption to niche or research-scale applications.

Catalyst: Ferric Nitrate

Fe(NO₃)₃ at 10 – 100 ppm provides the Fe³⁺ ions that enable the Fenton-type catalytic cycle described in Section 3. The catalyst loading must be optimized for each formulation: insufficient Fe³⁺ leaves the H₂O₂ utilization rate too low for the target MRR; excess Fe³⁺ destabilizes the slurry through uncontrolled particle flocculation and increases the risk of tungsten surface pitting from over-aggressive oxidation.

Complexing Agents and Stabilizers

Organic acids — citric acid, malonic acid, glycine, and oxalic acid among the most commonly used — serve as complexing agents and pH buffers. As complexing agents, they bind dissolved tungsten ions and ferric ions in soluble chelate complexes, preventing their re-precipitation as solid particles at the wafer surface or within the slurry delivery system. As pH buffers, they provide a stable chemical environment even as the polishing reaction produces acidic or basic byproducts. Surfactants may also be added at low concentrations to control abrasive dispersion stability and modify the tribological behavior of the slurry-pad interface.

6. Critical Performance Metrics

Qualifying a tungsten CMP slurry — whether for initial introduction or for ongoing supplier management — requires evaluating a defined set of performance parameters under controlled test conditions. These metrics form the common language between slurry suppliers and fab process engineers, and they determine whether a formulation is fit for a specific application.

Material Removal Rate (MRR)

MRR is expressed in Å/min (angstroms per minute) and measures how fast the slurry removes tungsten from a blanket film wafer under specified polishing conditions: platen rotation speed, wafer carrier (head) rotation speed, downforce (psi or kPa), slurry flow rate (mL/min), and temperature. A production-viable tungsten MRR for Step 1 bulk removal typically falls in the range of 1,500 to 4,000 Å/min, with some high-throughput formulations exceeding this range at elevated downforce. MRR must be measured consistently across multiple wafers in the same run to determine polish rate stability, and across multiple lots of slurry to assess lot-to-lot reproducibility.

Within-Wafer Non-Uniformity (WIWNU)

A high average MRR is of limited value if removal is non-uniform across the 300 mm wafer. WIWNU is typically specified as the standard deviation of the removal rate at multiple measurement sites across the wafer, normalized to the mean, expressed as a percentage (1σ). Production processes require WIWNU below 3 – 5%; leading-edge logic applications targeting contact recess uniformity below 20 Å across the wafer demand WIWNU below 2%.

Selectivity (W:Oxide MRR Ratio)

Selectivity is the ratio of the tungsten removal rate to the removal rate of the underlying dielectric (typically thermally grown SiO₂, TEOS-deposited SiO₂, or a low-k dielectric). High selectivity (e.g., 50:1) means tungsten is removed 50 times faster than oxide, effectively stopping the process at the W/Oxide interface. Step 1 slurries typically operate at selectivities of 25:1 to over 100:1. Step 2 buff slurries operate near 1:1 to 3:1. Selectivity is measured using blanket wafers of each material under identical CMP conditions.

ディッシング

Dishing is the concave depression that forms in the center of tungsten features after CMP. Measured in angstroms using a step height profiler or AFM on patterned test wafers, dishing occurs because the polishing pad can deflect slightly into the recess created by a large-diameter tungsten feature, over-removing tungsten relative to the surrounding oxide. Acceptable dishing tolerances are application-specific: sub-10 nm logic node contacts may require dishing below 50 Å; less demanding applications may tolerate up to 500 Å.

浸食

Erosion measures the loss of inter-layer dielectric material in high-density tungsten array test structures, where the collective effect of many tungsten plugs causes the polishing pad to remove more oxide than in low-density or isolated regions. It is measured as the difference in oxide height between isolated and dense array areas on a patterned metrology wafer, expressed in angstroms. Erosion directly reduces the electrical isolation between adjacent interconnect levels.

Defectivity

Post-CMP wafer inspection identifies defects in several categories: micro-scratches (linear surface damage from large abrasive particles or hard agglomerates); residue particles (incompletely rinsed slurry components); corrosion pits (local over-oxidation from hot spots in the slurry chemistry); and staining (ionic or organometallic contamination). Defect counts are measured per cm² using optical brightfield and darkfield scanning inspection systems. Leading-edge logic and memory applications specify post-clean defect levels in the single digits per cm² for yield-critical defect types.

7. Highly Selective vs. Low Selective Tungsten CMP Slurry

The selectivity of a tungsten CMP slurry — its ratio of tungsten material removal rate to oxide dielectric removal rate — is the single formulation parameter with the greatest impact on process outcome. Choosing the correct selectivity class for each step is not a matter of preference; it is a technical requirement dictated by the process architecture, the device geometry, and the yield targets of the application.

The practical implication is that most production flows run both: a high-selectivity slurry on Platen 1 (Step 1) and a non-selective slurry on Platen 2 (Step 2). Each is qualified independently, and process engineers optimize the time allocation between steps to balance the competing requirements of dielectric protection (favors Step 1 dominated) versus planarity and surface quality (favors adequate Step 2 time).

Selectivity is also a function of process conditions, not only slurry chemistry. Increasing downforce on a highly selective slurry can reduce effective selectivity by mechanically abrading oxide more aggressively; reducing downforce on a non-selective slurry can improve planarity outcome. This interdependence between slurry chemistry and process parameters is why complete process window characterization — not just a single-point datasheet specification — is essential for reliable production use.

8. Applications: Logic, 3D NAND, and DRAM

Tungsten CMP serves structurally different functions across logic, NAND flash, and DRAM device families, and each imposes distinct demands on slurry performance. A slurry formulation optimized for logic contact CMP may not be suitable for 3D NAND wordline applications, and vice versa. Understanding device-specific requirements is fundamental to slurry selection and supplier qualification.

Logic Devices: MOL Contact and Replacement Metal Gate

In high-performance logic chips — processors, GPUs, application processors, and AI accelerators fabricated at nodes from 28 nm down to sub-3 nm — tungsten CMP serves at the middle-of-line (MOL) level and at the replacement metal gate (RMG) step.

MOL contact formation fills the contact plugs that connect individual transistor terminals to the first metal interconnect layer (M0 or M1). At sub-7 nm nodes, contact diameters are below 15 nm with aspect ratios frequently exceeding 10:1. After CVD tungsten fill, the CMP step must clear the overburden with exceptional within-wafer uniformity (WIWNU <2%) and achieve a contact recess (dishing) below 50 Å — tolerances so tight that a 10 nm variation in process conditions can be the difference between passing and failing electrical probe results. The dielectric loss budget at these nodes is also severe: losing even 5 nm of ILD at the MOL level can affect the capacitance of neighboring structures and change device timing characteristics.

Replacement metal gate (RMG) CMP planarizes the tungsten (or tungsten composite) that fills the gate electrode trench after the sacrificial polysilicon gate is replaced. Gate height uniformity across the die — directly controlled by the CMP step — translates into threshold voltage uniformity across all transistors on the chip. A gate height non-uniformity of 1 nm can contribute tens of millivolts of V_th variation, which cascades into performance spread and test bin loss.

3D NAND Flash Memory

The transition to 3D NAND architecture introduced tungsten as the wordline conductor material, replacing the polysilicon wordlines used in planar NAND devices. In a 3D NAND gate stack, alternating layers of oxide and nitride are deposited on the wafer, the nitride is selectively removed, and tungsten is deposited to replace it as the wordline gate electrode. This process, repeated across 200 or more alternating layer pairs in current-generation devices, creates a CMP challenge unlike any other in semiconductor manufacturing.

Tungsten wordline CMP in 3D NAND must planarize a surface with dramatically varying pattern density: the array region contains dense, uniformly pitched tungsten wordlines, while the staircase region (where each successive wordline is exposed for contact formation) has a non-uniform step profile that extends across hundreds of micrometers. The slurry must deliver consistent removal across both regions simultaneously, maintaining planarity to within the tolerances needed for the subsequent via lithography step — which must land precisely on each wordline contact landing pad at each of the 200+ layer levels.

The cumulative mechanical stress on a 3D NAND gate stack during extended CMP also imposes constraints on slurry formulation and polishing conditions. Stack cracking or delamination from excessive pressure — even momentarily — can destroy the entire lot. Slurry formulations for 3D NAND applications are therefore optimized for lower downforce operation with enhanced chemical contribution to ensure adequate MRR without mechanical damage risk.

DRAM: Buried Wordline and Storage Node Contact

DRAM memory cells use tungsten in two key structures. The buried wordline (bWL) fills a narrow trench recessed below the active silicon surface; after tungsten deposition, CMP must clear the overburden and recess the tungsten to a precisely controlled depth within ±5 Å to ensure correct cell capacitance and avoid shorting to the silicon active area directly above. This is among the tightest depth-of-recess tolerances in production CMP anywhere in the semiconductor industry.

The storage node contact (SNC) fills the via connecting the bitline to the capacitor storage node. SNC CMP requirements are primarily driven by uniformity and surface cleanliness, as metal contamination from the tungsten fill or the slurry chemistry at this level can increase leakage current in the capacitor and degrade data retention time — the primary quality metric for DRAM memory cells.

9. How to Evaluate a Tungsten CMP Slurry Supplier

Qualifying a new tungsten CMP slurry supplier is a multi-month investment that spans technical performance assessment, supply chain evaluation, and commercial negotiation in parallel. The framework below reflects the criteria used by process engineering, materials procurement, and supply chain risk management teams at wafer fabs across the industry.

Technical Qualification Criteria

The technical qualification package from any candidate supplier should include, at minimum:

• Removal rate characterization: Tungsten MRR and oxide MRR data under standard CMP test conditions, with at minimum ±3σ statistical data across a qualification lot
• Selectivity data: W:Oxide ratio at nominal and boundary process conditions (downforce, speed, temperature)
• Dishing and erosion data: Measured on standard patterned test wafers (MIT, SKW, or application-specific pattern sets) at nominal and overpolish time conditions
• Defectivity characterization: Post-CMP and post-clean defect maps and defect count summaries by category, from optical brightfield and darkfield inspection systems
• Particle size distribution: Mean particle size, PSD width, and large-particle (tail) characterization by dynamic light scattering or laser diffraction
• Slurry stability data: MRR and defect performance as a function of storage time and temperature
• Metallic purity: ICP-MS data for key metallic impurities (Fe, Na, K, Ca, Cr, Ni, Cu, Zn) at or below low-ppb levels

Supply Chain and Operational Evaluation

Technical performance is a necessary but not sufficient condition for supplier qualification. Operational factors have equal importance in production environments where CMP slurry supply disruption can halt wafer production within hours:

• Geographic proximity and logistics capability: Shorter supply chains reduce lead times and reduce the risk of temperature excursion during transport for H₂O₂-containing formulations
• Minimum order quantity (MOQ) and delivery frequency: Especially important for smaller fabs or during technology ramp-up phases
• Batch-to-batch consistency certification: Certificate of Analysis (CoA) with every delivery, with specified acceptance criteria
• Safety data, regulatory compliance: SDS documentation, REACH/RoHS compliance, UN transport classification
• Application engineering support: Availability of process engineers who can assist with slurry integration, endpoint setup, and process excursion root-cause analysis

The Strategic Case for Supplier Diversification

The consolidation of the CMP consumables industry in recent years — most notably the merger of major players that concentrated significant market share with fewer Tier 1 vendors — has increased supply concentration risk for fabs that rely on a single supplier. As of 2026, a growing number of logic and memory fabs operate formal multi-vendor qualification policies for CMP slurries, maintaining two or more qualified sources for each application. This approach requires additional qualification investment upfront but provides supply assurance, pricing leverage, and the option to shift volume rapidly in response to supply disruptions or quality events.

10. Tungsten CMP Slurry Market in 2026

The global tungsten CMP slurry market is a segment of the broader CMP slurry market, which itself is part of the semiconductor process chemicals and consumables industry. In mid-2026, the tungsten CMP slurry market is valued at approximately USD 400 – 550 million annually, with compound annual growth rates projected at 4 – 6% through the end of the decade based on estimates from multiple industry research firms. This growth is driven by several structural demand factors.

AI and High-Performance Computing Demand

The rapid expansion of AI training and inference infrastructure has driven record wafer starts at leading logic foundries. AI accelerators and HPC chips are architecturally contact-intensive: a leading-edge GPU or AI chip may contain billions of individual tungsten contact plugs per die, each requiring a CMP step in its fabrication. Higher wafer volumes at logic fabs translate directly to higher tungsten CMP slurry consumption.

3D NAND Layer Count Scaling

As memory manufacturers continue scaling 3D NAND from 200 to 300 and beyond, the tungsten content per memory wafer increases proportionally and CMP polish times extend. Both effects increase per-wafer slurry consumption. The shift toward more complex 3D NAND architectures (dual-deck stacks, string stacking) further expands the number of CMP steps per wafer in memory manufacturing.

Automotive and Industrial Semiconductor Growth

Electrification of vehicles, expansion of advanced driver assistance systems (ADAS), and industrial automation are sustaining strong demand for mature-node power, analog, and microcontroller chips manufactured at 28 nm, 40 nm, and 65 nm nodes. These nodes use tungsten CMP intensively and do not transition to alternative metal systems, providing a stable demand base that runs parallel to leading-edge node growth.

Asia-Pacific Capacity Expansion

New fab construction across China, South Korea, Japan, and Taiwan represents the largest source of incremental CMP slurry demand globally. Asia-Pacific fabs are also the primary growth market for qualified alternative and regional suppliers, who can offer logistics advantages, faster technical support response, and competitive pricing compared to established Western-headquartered Tier 1 suppliers whose primary operations are geographically distant.

11. JEEZ Tungsten CMP Slurry Solutions

Jizhi Electronic Technology Co., Ltd. — operating under the JEEZ brand (jeez-semicon.com) — is a manufacturer of semiconductor consumables serving customers in logic, memory, and power device manufacturing worldwide. JEEZ’s product portfolio encompasses CMP polishing slurries, CMP polishing pads, dicing blades, and absorption and backing films, providing fab customers with a coordinated source for the consumables most critical to their CMP and dicing process steps.

JEEZ tungsten CMP slurries are formulated and characterized to address both steps of the standard two-step process architecture. The product offering includes two series:

Both series are available in sample quantities for process qualification, with full documentation packages including Safety Data Sheets (SDS), Certificates of Analysis (CoA), particle size distribution reports, and metallic impurity characterization by ICP-MS. JEEZ’s application engineering team provides technical consultation throughout the qualification process — from initial screening and test wafer design to process window optimization and production readiness review.