CMP Materials for Advanced Nodes (Below 14 nm)

1. Why Advanced Nodes Demand More from CMP Materials

The transition from planar CMOS to FinFET, and now to Gate-All-Around (GAA) nanosheet transistors, has not simply shrunk device dimensions — it has fundamentally transformed the geometric, chemical, and mechanical environment in which CMP must operate. Each successive architecture introduces new materials, tighter removal budgets, and higher step-count requirements that push standard CMP consumables beyond their design envelope.

Three fundamental shifts make advanced-node CMP categorically harder than mature-node CMP:

• Tighter removal budgets: At sub-7 nm, the vertical feature budgets for each film are measured in single-digit nanometers. A CMP step that overshoots its target by 5 nm at 28 nm is a minor process annoyance; the same overpolish at 3 nm can completely consume a metal liner or damage the underlying device structure. This demands endpoint precision and slurry selectivity that earlier generations of consumables were never designed to provide.
• Novel material systems: Each new node introduces metals (Co, Ru, Mo) and dielectrics (SiOC, SiCN, hafnium-based high-k films) for which standard CMP slurries were not formulated. A new CMP chemistry must be developed — often from scratch — for each new material, a process that can take 2–4 years of R&D for a truly novel application.
• Mechanical fragility of advanced structures: Ultra-low-k dielectrics have Young’s moduli as low as 2–5 GPa — orders of magnitude below the 70 GPa of thermal SiO₂. High-aspect-ratio 3D NAND structures and thin-film transistors in stacked 3D-IC integration can delaminate under CMP downforce levels that are routine for conventional planar processes.

2. CMP Challenges in FinFET Architecture (14–7 nm)

FinFET technology, introduced in volume production at 22 nm (Intel) and 16/14 nm (TSMC, Samsung), introduced a non-planar transistor geometry that immediately created new CMP challenges. The fin structures — narrow silicon pillars rising above the substrate surface — must survive CMP steps intended to planarize the surrounding dielectric material. Any lateral stress or excessive downforce during fin-area ILD CMP can damage or delaminate the fin structures themselves.

Key FinFET CMP Steps and Consumable Requirements

The introduction of cobalt as the contact metal at 7 nm (replacing tungsten for the most advanced contacts) was one of the most significant CMP chemistry transitions of the FinFET era. Cobalt’s lower hardness and sensitivity to galvanic corrosion required entirely new slurry formulations. For a detailed treatment of cobalt CMP chemistry, see Section 4 of this article and the broader slurry chemistry discussion in our CMP Slurry Types, Applications & Selection Guide.

3. Gate-All-Around (GAA) and CMP at 3 nm and Below

Gate-All-Around (GAA) nanosheet transistors, currently in volume production at TSMC (N3), Samsung (3GAE), and Intel Foundry (18A), represent the most complex transistor geometry in semiconductor history. In GAA, horizontal silicon or SiGe nanosheets (typically 4–8 nm thick, stacked vertically in groups of 2–4) are completely surrounded by the gate dielectric and metal on all four sides — enabling superior electrostatic control but requiring extraordinary precision in the CMP steps that reveal, isolate, and planarize these structures.

Nanosheet Reveal CMP: The Most Demanding Planarity Step in Semiconductor Manufacturing

The nanosheet reveal step removes the SiO₂ or SiOC isolation fill deposited between GAA cell rows, stopping on the topmost nanosheet surface with a target residual film thickness tolerance of ±1–2 nm across the full 300 mm wafer. Achieving this requires:

• Nano-ceria slurry with D99 particle size below 100 nm to minimize nanosheet surface damage
• Extremely high SiO₂:Si₃N₄ and SiO₂:SiGe selectivity to preserve the topmost nanosheet surface and sidewall spacer
• Tight within-wafer MRR uniformity (<1.5% 1σ) to ensure no nanosheet surface is over-polished while residuals remain on the opposite side of the wafer
• Real-time optical endpoint detection with sub-nm sensitivity to stop the CMP step before the tolerance budget is exhausted

4. Cobalt CMP: Chemistry, Challenges, and Defect Control

Cobalt has emerged as the preferred contact and local interconnect metal for advanced logic nodes at 7 nm and below, replacing tungsten for the most demanding applications due to its lower bulk resistivity at sub-20 nm feature sizes. However, cobalt’s physical and chemical properties create a very different and considerably more challenging CMP environment than tungsten.

Why Cobalt CMP Is Harder Than Tungsten CMP

• Cobalt is much softer than tungsten (Vickers hardness ~1,000 MPa for Co vs. ~3,430 MPa for W), meaning abrasive contact forces that are routine for W CMP can produce dishing or scratches on cobalt surfaces.
• Cobalt is susceptible to galvanic corrosion at interfaces with dissimilar metals (particularly TiN barrier metal). In the presence of an oxidizing slurry, electrochemical potential differences between Co and TiN can drive anodic dissolution of cobalt at the contact perimeter — creating pitting defects that are not observable by standard optical inspection but degrade contact resistance and reliability.
• Cobalt ion contamination (Co²⁺, Co³⁺) leached from the polished surface into the slurry bath is a source of metal contamination on wafer surfaces if not removed by post-CMP clean. Co is a deep-level trap in silicon and can cause serious device leakage if present at the transistor level.

Cobalt CMP Slurry Design Principles

Effective cobalt CMP slurry formulation requires balancing three competing requirements: sufficient oxidation of the cobalt surface to generate an abradable CoO/Co(OH)₂ layer (for adequate MRR), corrosion inhibition at the Co/TiN galvanic interface (to prevent pitting), and complexation of dissolved cobalt ions (to prevent re-deposition). The typical solution is:

• Mild oxidizer (H₂O₂ at 0.5–2 wt%, or periodate at low concentration) — moderate enough to form Co oxide without driving runaway corrosion
• Cobalt-specific corrosion inhibitors (imidazole, benzotriazole derivatives, or proprietary heterocyclic compounds) that adsorb preferentially on Co surfaces in contact with TiN
• Organic acid complexants (citric acid, malic acid) to solubilize Co ions and prevent re-deposition
• Ultra-low defect colloidal silica (20–50 nm, D99 <150 nm) as the abrasive, operated at pH 4–7

5. Ruthenium CMP: The Emerging Frontier

Ruthenium (Ru) is positioned as the next-generation metal for contacts, local interconnects, and gate fill at sub-5 nm nodes. Its advantages over cobalt include lower resistivity at nanometer dimensions, better thermal stability (Ru melting point: 2,334 °C vs. Co 1,495 °C), and improved compatibility with high-k gate dielectrics. Several leading foundries have disclosed Ru-based metallization schemes for their 2 nm and beyond process generations.

The Challenge of Ruthenium’s Chemical Inertness

Ruthenium is thermodynamically noble under most aqueous conditions — much more so than copper or cobalt. This chemical inertness, which is an advantage for device reliability, is a significant obstacle for CMP, where chemical reactivity of the target surface is a prerequisite for effective material removal. Standard copper and cobalt CMP slurries (H₂O₂-based, moderately acidic) achieve negligible MRR on Ru surfaces.

Effective Ru oxidation requires either very strong oxidizers at low pH (periodate, bromate, or Ce⁴⁺ species at pH 1–3) or electrochemical assistance. The primary oxidation product, RuO₄ (ruthenium tetroxide), is a volatile, toxic compound that can form at high oxidizer concentrations and temperatures, creating both process safety and contamination concerns. Managing the RuO₄ formation risk while maintaining adequate Ru MRR is the central challenge of Ru CMP chemistry development.

As of April 2026, Ru CMP chemistry is actively transitioning from laboratory demonstration to process qualification at leading-edge fabs. JEEZ is engaged in Ru slurry R&D and welcomes collaborative development partnerships with fabs working on Ru integration. Contact us to discuss your requirements.

6. Molybdenum CMP for GAA Gate Fill

Molybdenum (Mo) is attracting strong interest as an alternative metal fill for GAA transistor gates, where its workfunction near mid-gap, good thermal stability, and lower gate resistance compared to tungsten at small dimensions make it competitive. Intel has disclosed Mo gate fill in their 18A process; other foundries are evaluating it for sub-2 nm generations.

Mo CMP chemistry is distinctly different from other metal CMP applications. Molybdenum oxide (MoO₃) dissolves readily in alkaline solution (forming MoO₄²⁻), which creates an unusual situation: a strongly alkaline slurry can achieve high Mo MRR purely through chemical dissolution, without requiring aggressive abrasion. However, this same solubility creates dishing risk in wide Mo features if the chemical etch rate is not carefully controlled by surface-blocking additives.

Acidic oxidizing slurries (pH 2–4 with peroxydisulfate or periodate) can also be used for Mo CMP, converting Mo to MoO₂ or MoO₃ surface layers that are mechanically removable. The choice between alkaline-dissolution and acidic-oxidation chemistry depends on the specific selectivity requirements of the gate stack — particularly the need to stop cleanly on the high-k gate dielectric without thinning it.

7. Ultra-Low-k Dielectric CMP: Mechanical Fragility and Selectivity

The progressive reduction in dielectric constant (k) required to reduce RC delay in BEOL interconnects has produced a family of ultra-low-k (ULK) porous dielectric films with Young’s moduli as low as 2–5 GPa and fracture toughnesses approaching those of aerogels. CMP of copper and barrier metals in these fragile dielectric environments is one of the most technically demanding processes in advanced logic manufacturing.

Failure Modes Specific to Ultra-Low-k CMP

• Dielectric delamination: The interface between the ULK film and the etch stop (typically SiCN or SiCO) is the weakest mechanical plane in the entire interconnect stack. Excessive CMP downforce or lateral shear stress can cause interface delamination that propagates laterally, creating voids in the interconnect layer.
• Cohesive fracture within the dielectric: For the most porous ULK films (k < 2.2), the film itself can fracture cohesively under downforce, creating a rough, cracked surface that cannot be recovered by subsequent processing.
• Slurry infiltration into open pores: If the slurry’s liquid phase wets and penetrates the open pore network of the ULK material, it can carry abrasive particles and metal ions into the film’s interior — causing dielectric constant increase, leakage, and reliability degradation.

The standard mitigation approach for ULK CMP combines low-downforce process conditions (typically <1.5 psi wafer pressure), soft polishing pads with low modulus, and slurry formulations with low abrasive concentration and surfactant systems that reduce slurry infiltration into open pores. These constraints severely limit the available MRR and require careful endpoint control to compensate for the reduced process margin.

8. CMP for 3D NAND: High Aspect Ratio and Multi-Layer Demands

3D NAND flash memory, which stacks memory cells vertically in layer counts ranging from 96 layers (2019 vintage) to 300+ layers (leading products in 2026), requires CMP at multiple points in the fabrication sequence. The most challenging CMP steps in 3D NAND involve planarizing the alternating oxide-nitride (ON) or oxide-polysilicon stack after each tier deposition, and removing tungsten or molybdenum wordline fill material after the gate-replacement process.

9. 3D-IC and Hybrid Bonding: The Sub-Nanometer Roughness Challenge

Hybrid bonding is the enabling technology for the highest-density 3D-IC integration — used in High-Bandwidth Memory (HBM), CMOS Image Sensors (CIS), and advanced logic-on-logic stacking. In hybrid bonding, two wafers are joined through direct dielectric-to-dielectric contact (SiO₂ or SiCN bonding surfaces) and Cu-to-Cu metal pad contact, without any adhesive or solder intermediate layer. The bond forms through surface chemistry and thermal activation, and its quality depends critically on the planarity and roughness of both bonding surfaces.

CMP Specifications for Hybrid Bonding Layer Preparation

Meeting these specifications requires ultra-pure, sub-30 nm colloidal silica slurries at concentrations below 2 wt%, combined with soft polishing pads operating at ultra-low downforce (<1 psi). Extended multi-step post-CMP cleaning — typically including SC1 (APM), DHF, and megasonic rinse — is mandatory to achieve the surface particle and metal contamination targets.

For slurry selection guidance in this application, see our article on CMP Abrasives: Ceria vs. Silica vs. Alumina, particularly the colloidal silica section covering bonding-grade ultra-pure variants.

10. CMP Materials Roadmap: 2026 to 2030

11. FAQ

What is the difference between CMP requirements at 7 nm vs. 3 nm?

The 7 nm node primarily introduced cobalt contacts and tighter selectivity requirements for STI and ILD CMP. At 3 nm (GAA architecture), the challenges escalate dramatically: CMP must now handle nanosheet reveal with sub-2 nm vertical precision, gate fill with novel metals (Ru or Mo), and ultra-low-k dielectric environments with Young’s moduli below 5 GPa. The number of CMP steps also increases by approximately 30–40% between 7 nm and 3 nm, compounding the cost and yield implications of each per-step performance gap.

Can standard CMP slurries be used for cobalt and ruthenium?

No. Standard copper or tungsten CMP slurries are not suitable for cobalt or ruthenium. Cobalt requires specially formulated slurries with cobalt-specific corrosion inhibitors and mild oxidizers balanced against galvanic corrosion risk at Co/TiN interfaces. Ruthenium requires strongly oxidizing acidic chemistries (periodate or Ce⁴⁺ based) that are completely different from any other commercial CMP application. Using the wrong slurry chemistry on these metals risks severe defect events, contamination, or complete inability to remove the film within the process time budget.

What makes hybrid bonding CMP different from standard copper CMP?

The fundamental difference is the surface quality requirement. Standard copper BEOL CMP targets dishing <20–30 nm and scratch counts in the tens per wafer. Hybrid bonding CMP must achieve Cu dishing below 5 nm, surface roughness below 0.3 nm Ra, and fewer than 10 particles per wafer above 50 nm — specifications that are 5–10× tighter than conventional CMP on every metric. Achieving these targets requires ultra-dilute nano-silica slurries, soft polishing pads at ultra-low downforce, and multi-step post-CMP cleaning sequences that are more akin to wafer cleaning than to conventional CMP cleanup.

How many CMP steps does a 3 nm logic wafer require?

A fully processed 3 nm logic wafer (including FEOL, MOL, and BEOL through the final metallization layer) requires approximately 50–70 CMP process steps, depending on the specific process flow and integration scheme. This compares to approximately 30–40 steps at 10 nm, 15–20 steps at 28 nm, and fewer than 10 at 180 nm. Each additional CMP step represents an opportunity for yield loss from defects, non-uniformity, or contamination, which is why advanced-node CMP consumable performance standards are so much more stringent than at mature nodes.