Two-Step Copper CMP: Bulk Cu vs. Barrier Slurry — Chemistry, Selectivity & Endpoint Detection
The two-step copper CMP process is the universal architecture for copper interconnect planarization in production semiconductor manufacturing. Step 1 rapidly removes the bulk copper overburden; Step 2 precisely clears the barrier metal while stopping on the ILD. These two objectives demand fundamentally different slurry chemistries, polishing pressures, and endpoint detection strategies — and correctly integrating both steps is critical to achieving low dishing, low erosion, and complete barrier clearance simultaneously. This article explains the chemistry, selectivity requirements, and endpoint detection methods for each step, with practical guidance for process integration.
Índice
1. Why Two Steps Are Necessary
A single copper CMP slurry optimized for bulk copper removal is fundamentally incompatible with the requirements for precise barrier metal clearing. This incompatibility arises from three independent constraints that cannot be simultaneously satisfied in one formulation:
- Removal rate vs. selectivity: High-rate Step 1 slurries use aggressive oxidizer concentrations and hard abrasives to remove 400–800 nm of copper overburden quickly — but these same conditions also remove ILD material rapidly, producing severe erosion during Step 2’s barrier-clearing phase. A Step 2 process using Step 1 chemistry would erode the ILD by 50–100 nm before clearing barrier in dense array regions.
- Barrier attack: The barrier metals — tantalum (Ta), tantalum nitride (TaN), cobalt (Co), or ruthenium (Ru) — are significantly harder and more chemically resistant than copper. Step 1 chemistry, tuned to dissolve copper rapidly, has little to no effectiveness on Ta or TaN. Attempting to clear barrier with Step 1 slurry requires extremely long polishing that massively over-polishes the copper features.
- Endpoint detection compatibility: The endpoint signal for “stop at the copper-barrier interface” (Step 1 endpoint) is physically different from the signal for “barrier is cleared, stop on ILD” (Step 2 endpoint). Two separate detection events require two separate process steps with distinct monitoring configurations.
The two-step architecture solves these incompatibilities cleanly: Step 1 handles high-rate copper removal with no concern for ILD erosion (there is no exposed ILD yet), and Step 2 handles barrier clearing with a slurry optimized for selectivity and low mechanical stress.
2. Step 1: Bulk Copper Removal
Step 1 Chemistry and Objectives
Step 1 must remove 400–800 nm of electroplated copper overburden as rapidly as possible while maintaining WIWNU below 5% across the 300 mm wafer. The stopping condition for Step 1 is not the barrier metal surface — it is a target remaining copper thickness of 20–50 nm above the barrier, leaving a thin, uniform copper residual that Step 2 can clear precisely without introducing planarity disturbance.
| Parámetro | Step 1 Target | Rationale |
|---|---|---|
| Cu Removal Rate | ≥300 nm/min (at 2–3 psi) | Minimize polishing time for throughput |
| Abrasive Type | Alumina or fumed silica | High hardness for aggressive Cu removal |
| H₂O₂ Concentration | 2–5 wt% | Rapid Cu surface oxidation |
| WIWNU (1σ) | <5% | Uniform residual Cu for Step 2 entry |
| Step 1 End Point | 20–50 nm Cu above barrier | Prevent early barrier exposure; enable Step 2 uniformity |
| Defect Density | <50/cm² (0.1 µm+) | Step 2 will partially clean; some step 1 defects tolerated |
Step 1 slurry abrasives are typically fumed or colloidal alumina (20–80 nm primary particle size) for maximum removal rate. At advanced nodes where ELK dielectric stacks limit pressure to <1 psi, engineered colloidal silica with chemically enhanced formulations (higher H₂O₂, optimized glycine loading) is increasingly used to compensate for the mechanical throughput limitation. JEEZ’s CuB series covers this full range with alumina-based formulations for conventional nodes and colloidal-silica enhanced variants for ELK-compatible Step 1 at advanced nodes.
Step 1 Endpoint: Stopping at the Right Thickness
Stopping Step 1 with 20–50 nm of uniform copper remaining is critical. Too much residual copper (>80 nm) creates a Step 2 entry condition that is too thick for the gentler Step 2 chemistry to clear in reasonable polishing time, risking dishing on wide features from extended Step 2 polishing. Too little residual copper (<10 nm or direct barrier exposure) creates a kinetic discontinuity that disturbs planarity and risks ILD damage in Step 2.
Eddy-current sensing is the preferred Step 1 endpoint detection method: non-contact electromagnetic induction probes embedded in the platen measure copper film sheet resistance in real time through the pad, providing a thickness reading that directly tracks the approach to the 20–50 nm target. Closed-loop APC systems adjust Step 1 polishing time run-to-run based on the measured endpoint time from the previous wafer, compensating for lot-to-lot ECD thickness variation.
3. Step 2: Barrier Clearing & Final Planarization
Step 2 Chemistry Requirements
Step 2 must simultaneously accomplish three tasks that require carefully balanced competing chemistry: clear the thin (~20–50 nm) copper residual from Step 1, remove the barrier metal (Ta/TaN or Co/Ru) that now separates the copper lines, and stop on the ILD without excessive erosion. The key formulation requirements are:
High Cu:ILD Selectivity
Copper removal rate should far exceed ILD removal rate — ideally >50:1 — to limit dielectric erosion in dense metal arrays during the barrier clearing period.
Adequate Barrier Rate
Barrier (Ta, TaN, Co, Ru) removal rate of 10–30 nm/min is needed for economically viable Step 2 cycle time without excessive ILD attack during barrier clearing.
Low Static Etch Rate
SER <0.5 nm/min to protect copper in completed trench features from dishing during the longer Step 2 polishing time required for barrier clearing.
Step 2 slurries universally use colloidal silica abrasives (D50 60–120 nm) rather than alumina, for their lower hardness and higher surface selectivity. The pH is shifted toward near-neutral (6–8) compared to Step 1 to improve both Cu:ILD selectivity and barrier metal compatibility. BTA concentration is typically reduced relative to Step 1 to allow adequate barrier attack, while oxidizer concentration is modulated to provide copper and barrier oxidation without ILD attack.
Ta/TaN vs. Co/Ru Barrier Compatibility
Standard Step 2 formulations are optimized for Ta/TaN barrier systems. Cobalt (Co) and ruthenium (Ru) liners — increasingly used at 7 nm and below — have very different electrochemical behavior: they corrode aggressively in acidic oxidizing environments and form galvanic couples with copper that accelerate liner dissolution. JEEZ CuS barrier slurries include dedicated Co/Ru-compatible variants with near-neutral pH formulations and Co/Ru-specific corrosion inhibitor packages.
For a detailed treatment of galvanic corrosion at Cu/Co and Cu/Ru interfaces, see: Corrosion Inhibitors in Copper CMP Slurry: BTA Mechanism, Galvanic Risks & Alternatives.
4. Optional Step 3: Buff Polish
A third polishing step — a light “buff” using dilute colloidal silica or an abrasive-free colloidal solution — is increasingly used in advanced-node logic (7 nm and below) and leading-edge DRAM processes. Step 3 serves two functions:
- Planarity restoration: Step 2 can introduce local topographic non-uniformity at the transition from copper-rich to copper-lean regions. A brief Step 3 buff on a soft pad with high Cu:ILD selectivity (often >200:1) selectively removes residual topographic peaks without affecting the now-planar ILD surface below.
- Surface quality improvement: Step 3 removes residual Step 2 BTA-Cu surface film, reduces surface roughness to Ra <0.3 nm rms, and reduces Step 2 scratch defect count by light mechanical re-polishing at very low pressure (<0.5 psi).
Step 3 is not universal — the additional cycle time and tool footprint cost means it is typically reserved for the most critical metal levels (M1, M2) where planarity and surface quality specifications are tightest.
5. Endpoint Detection Methods
Endpoint detection is the technical foundation of the two-step copper CMP process. Each step requires a different endpoint event to be detected reliably at production throughput with millisecond-level temporal resolution.
Eddy-Current Sensing (Step 1 Thickness Control)
Electromagnetic induction coils in the platen generate an alternating field that induces eddy currents in the conducting copper film. The impedance change of the coil circuit correlates with copper film sheet resistance and therefore thickness. This provides real-time thickness tracking with ~1 nm resolution, enabling closed-loop Step 1 stop-on-thickness control. Eddy-current endpoint is the most accurate and APC-friendly method for Step 1 control at advanced nodes.
In-Situ Optical Reflectance (Step 1/Step 2 Transition)
A laser or broadband light source illuminates the wafer through a window in the platen during polishing. As the copper film thins toward the barrier and then clears, the reflectance spectrum changes detectably — copper has a characteristic reflectance peak at ~570 nm that diminishes as the surface transitions to the lower-reflectance barrier metal. Optical reflectance monitoring (ORM/ISRM) provides a clear endpoint signal at the Step 1/Step 2 transition and is useful as a backup to eddy-current sensing or as the primary method where eddy-current is unavailable.
Motor Current / Friction Monitoring (Step 2 Barrier Endpoint)
The torque required to rotate the polishing platen changes measurably when the surface composition transitions from copper (low friction with the pad) to barrier metal (higher friction, particularly for hard Ta and TaN) and then to ILD oxide (different friction coefficient again). Motor current monitoring provides a clear endpoint signal at the barrier clearance event — the moment when all barrier metal on the wafer has been removed and the pad is in contact with ILD only. This is the most widely used Step 2 endpoint method due to its simplicity and the clarity of the friction signal at the barrier-to-ILD transition.
6. Process Window Management & APC Integration
Managing the process window across a two-step sequence — ensuring that Step 1 consistently delivers the 20–50 nm copper residual target, and that Step 2 endpoint occurs within a tight over-polish window — requires robust APC integration.
A production copper CMP APC system typically implements:
- Run-to-run Step 1 time adjustment: Using the measured eddy-current endpoint time from the previous wafer, APC adjusts the Step 1 polishing time for the current wafer to hit the target residual copper thickness, compensating for lot-to-lot ECD thickness variation (typically ±5–15% of nominal).
- Step 2 over-polish time control: The Step 2 motor current endpoint time is measured per wafer, and the over-polish time (fixed seconds after endpoint detection) is validated against the target dishing budget. If the endpoint signal quality degrades (e.g., from pad glazing), APC flags the run for engineering review.
- Pad-aging compensation: Both Step 1 removal rate and Step 2 barrier clearing rate decrease as the pad ages. APC systems model pad-age-dependent removal rate curves and automatically compensate polishing time to maintain endpoint targets across the full pad lifetime (typically 300–600 wafers).
JEEZ application engineers assist customers in calibrating APC models for specific CuB/CuS slurry combinations — providing removal rate characterization data, pad aging curves, and endpoint signal characterization across the full slurry qualification matrix.
7. Frequently Asked Questions
Why can’t the same slurry be used for both Step 1 and Step 2?
Step 1 requires high removal rate, aggressive abrasives, and high oxidizer loading — conditions that would cause severe ILD erosion if continued through barrier clearing. Step 2 requires high Cu:ILD selectivity, gentler abrasives, and near-neutral pH to clear barrier without attacking the ILD — conditions that are too gentle and slow for efficient bulk copper removal in Step 1. No single formulation can simultaneously satisfy both sets of requirements at production-viable process conditions.
What happens if Step 1 exposes the barrier metal prematurely?
Premature barrier exposure — polishing Step 1 past the 20–50 nm copper residual target — creates two problems. First, the sudden change in polishing dynamics at the copper-to-barrier transition (barrier is much harder and less polishable than copper) creates a kinetic “shock” that disturbs planarity, leaving residual copper in some regions and over-exposing ILD in others. Second, the exposed barrier contacts the aggressive Step 1 chemistry before Step 2 begins, potentially causing barrier corrosion or galvanic attack at the Cu/barrier interface. Tight endpoint control is the primary mitigation.
Is a three-step Cu CMP process common in production?
A third buff step is increasingly common in advanced-node logic (7 nm and below) and leading DRAM production, but is not universally used. It is typically reserved for the lowest metal levels (M1, M2) where planarity and surface quality specifications are most stringent. At older nodes (28 nm and above) or less critical metal levels, a two-step process is generally sufficient and the additional cost of a third step is not justified by the yield benefit.
How does the transition from Ta/TaN to Co/Ru barriers affect two-step slurry selection?
Transitioning to Co or Ru liners requires a reformulated Step 2 slurry. Co and Ru are more susceptible to corrosion than Ta in oxidizing acidic conditions, and they form galvanic couples with copper that accelerate liner dissolution. Co/Ru-compatible Step 2 slurries use near-neutral pH (6.5–7.5), moderated H₂O₂ concentration, and Co/Ru-specific corrosion inhibitor packages. The Step 1 slurry can typically remain unchanged if Co/Ru is used only as a liner (not exposed during bulk Cu removal), but must be re-evaluated if the liner is exposed at any point during Step 1.
Optimizing Your Two-Step Copper CMP Process?
Jizhi Electronic Technology Co., Ltd. (JEEZ) supplies matched CuB + CuS slurry pairs for the full two-step copper CMP process, with Co/Ru-compatible variants for advanced-node barrier integration. Our application engineering team provides process window characterization and APC model support.
Contact JEEZ Application Engineering →
